A new built-in TPG method for circuits with random pattern resistant faults
| dc.contributor.author | Kavousianos, X. | en |
| dc.contributor.author | Bakalis, D. | en |
| dc.contributor.author | Nikolos, D. | en |
| dc.contributor.author | Tragoudas, S. | en |
| dc.date.accessioned | 2015-11-24T17:00:16Z | |
| dc.date.available | 2015-11-24T17:00:16Z | |
| dc.identifier.issn | 0278-0070 | - |
| dc.identifier.uri | https://olympias.lib.uoi.gr/jspui/handle/123456789/10735 | |
| dc.rights | Default Licence | - |
| dc.subject | built-in self-test | en |
| dc.subject | test pattern generators | en |
| dc.subject | on-a-chip | en |
| dc.subject | bist | en |
| dc.title | A new built-in TPG method for circuits with random pattern resistant faults | en |
| heal.abstract | The partition of the inputs of a circuit under test (CUT) into groups of compatible inputs reduces the size of a test pattern generator and the length of the test sequence for built-in self-test (BIST) applications. In this paper, a new test-per-clock BIST scheme is proposed which is based on multiple input partitions. The test session consists of two or more phases, and a new grouping is applied during each test phase. Using the proposed method a CUT can be tested at-speed and complete fault coverage (100%) is achieved with a small number of test vectors and small area overhead. Our experiments show that the proposed technique compares favorably to the already known techniques. | en |
| heal.access | campus | - |
| heal.fullTextAvailability | TRUE | - |
| heal.journalName | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | en |
| heal.journalType | peer reviewed | - |
| heal.language | en | - |
| heal.publicationDate | 2002 | - |
| heal.recordProvider | Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής | el |
| heal.type | journalArticle | - |
| heal.type.el | Άρθρο Περιοδικού | el |
| heal.type.en | Journal article | en |
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