Development of trigger systems and algorithms for the CMS experiment at the HL-LHC at CERN

dc.contributor.authorAdamidis, Kosmasen
dc.contributor.authorΑδαμίδης, Κοσμάςel
dc.date.accessioned2024-04-29T10:41:07Z
dc.date.available2024-04-29T10:41:07Z
dc.identifier.urihttps://olympias.lib.uoi.gr/jspui/handle/123456789/37542
dc.identifier.urihttp://dx.doi.org/10.26268/heal.uoi.17253
dc.rightsCC0 1.0 Universal*
dc.rights.urihttp://creativecommons.org/publicdomain/zero/1.0/*
dc.subjectParticle physicsen
dc.subjectDetectorsen
dc.subjectCERNen
dc.subjectCMSen
dc.subjectFPGAen
dc.subjectVHDLen
dc.subjectOptical fibersen
dc.titleDevelopment of trigger systems and algorithms for the CMS experiment at the HL-LHC at CERNen
dc.titleΑνάπτυξη συστημάτων και αλγορίθμων σκανδαλισμού για το πείραμα CMS στον επιταχυντή HL-LHC του CERNel
dc.typedoctoralThesisen
heal.abstractThe CMS experiment is being prepared for the Phase-2 era, when the High-Luminosity LHC (HL-LHC) will start its operations delivering more than 7 times the nominal LHC Luminosity. The aim of the CMS upgrade is both to maintain but also improve the detector performance, in order to extend the discovery reach of the detector. The amount and density of data produced by HL-LHC demands new detector systems, replacement of the majority of the on-detector electronics, and complete replacement of the Trigger system. The work of this thesis is part of the CMS Level-1 Trigger upgrade.The first part of the work was devoted to the development of an optical link protocol, operating at 25 Gbps and targeting FPGAs produced by Xilinx. The protocol will be the standard Phase-2 protocol, used by the Level-1 Trigger processors for their internal data exchange. A detailed description of its firmware implementation, as well as results of extended testing are presented. Moreover, the work here includes firmware developments that target the Barrel Muon Trigger Layer-1 subsystem, responsible for the generation of track segments of muons that cross the barrel region of CMS. An ATCA card based on a VU13P FPGA was designed to instrument this system. The design of certain modules of this card, as well as the development of its firmware infrastructure and the slice tests that demonstrated its performance using data from proton-proton collisions are presented in the second part of this thesis.en
heal.academicPublisherΠανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Φυσικήςel
heal.academicPublisherIDuoiel
heal.accessfreeel
heal.advisorNameΦούντας, Κωνσταντίνοςel
heal.committeeMemberNameΜάνθος, Νικόλαοςel
heal.committeeMemberNameΦούντας, Κωνσταντίνοςel
heal.committeeMemberNameΕυαγγέλου, Ιωάννηςel
heal.committeeMemberNameBachtis, Michailen
heal.committeeMemberNameΧριστοφιλάκης, Βασίλειοςel
heal.committeeMemberNameΠαπαδόπουλος, Ιωάννηςel
heal.committeeMemberNameΤσιατούχας, Γεώργιοςel
heal.dateAvailable2024-04-29T10:42:07Z
heal.fullTextAvailabilitytrue
heal.languageenel
heal.numberOfPages191el
heal.publicationDate2023-12
heal.recordProviderΠανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημώνel
heal.typedoctoralThesisel
heal.type.elΔιδακτορική διατριβήel
heal.type.enDoctoral thesisen

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