A design technique for energy reduction in NORA CMOS logic
| dc.contributor.author | Limniotis, K. | en |
| dc.contributor.author | Tsiatouhas, Y. | en |
| dc.contributor.author | Haniotakis, T. | en |
| dc.contributor.author | Arapoyanni, A. | en |
| dc.date.accessioned | 2015-11-24T17:01:20Z | |
| dc.date.available | 2015-11-24T17:01:20Z | |
| dc.identifier.issn | 1057-7122 | - |
| dc.identifier.uri | https://olympias.lib.uoi.gr/jspui/handle/123456789/10909 | |
| dc.rights | Default Licence | - |
| dc.subject | charge recycling | en |
| dc.subject | low-power design | en |
| dc.subject | no race (nora) cmos circuits | en |
| dc.subject | recycling differential logic | en |
| dc.subject | power | en |
| dc.title | A design technique for energy reduction in NORA CMOS logic | en |
| heal.abstract | In this work, a design technique to reduce the energy consumption in NO RAce (NORA) circuits is presented. The technique is based on a unidirectional switch topology combined with a new clocking scheme permitting both charge recycling between circuit nodes and elimination of the short circuit current. Calculations proved that energy savings higher than 20 % can be achieved. Simulation results from NORA designs in a 0.18-mu m CMOS technology are presented to demonstrate the effectiveness of the proposed technique to achieve both energy and energy-delay product reduction. | en |
| heal.access | campus | - |
| heal.fullTextAvailability | TRUE | - |
| heal.identifier.primary | Doi 10.1109/Tcsi.2006.885690 | - |
| heal.journalName | Ieee Transactions on Circuits and Systems I-Regular Papers | en |
| heal.journalType | peer reviewed | - |
| heal.language | en | - |
| heal.publicationDate | 2006 | - |
| heal.recordProvider | Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής | el |
| heal.type | journalArticle | - |
| heal.type.el | Άρθρο Περιοδικού | el |
| heal.type.en | Journal article | en |
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