A Built-In-Test Circuit for RF Differential Low Noise Amplifiers
| dc.contributor.author | Dermentzoglou, L. E. | en |
| dc.contributor.author | Arapoyanni, A. | en |
| dc.contributor.author | Tsiatouhas, Y. | en |
| dc.date.accessioned | 2015-11-24T17:02:17Z | |
| dc.date.available | 2015-11-24T17:02:17Z | |
| dc.identifier.issn | 1549-8328 | - |
| dc.identifier.uri | https://olympias.lib.uoi.gr/jspui/handle/123456789/11036 | |
| dc.rights | Default Licence | - |
| dc.subject | built-in-test (bit) | en |
| dc.subject | design for testability | en |
| dc.subject | lna testing | en |
| dc.subject | rf testing | en |
| dc.subject | triple modular redundancy | en |
| dc.subject | low-cost test | en |
| dc.subject | self-test | en |
| dc.subject | analog | en |
| dc.title | A Built-In-Test Circuit for RF Differential Low Noise Amplifiers | en |
| heal.abstract | This paper presents an efficient, low-cost, built-in test (BIT) circuit for radio frequency differential low noise amplifiers (DLNAs). The BIT circuit detects amplitude alterations at the outputs of the DLNA, due to parametric or catastrophic faults, and provides a single digital Pass/Fail indication signal. A triple modular redundancy approach has been adopted for the BIT circuit design to avoid possible yield loss in case of a malfunctioning test circuitry. The technique has been evaluated on a typical CMOS RF DLNA and simulation results are presented. | en |
| heal.access | campus | - |
| heal.fullTextAvailability | TRUE | - |
| heal.identifier.primary | Doi 10.1109/Tcsi.2009.2035417 | - |
| heal.journalName | Ieee Transactions on Circuits and Systems I-Regular Papers | en |
| heal.journalType | peer reviewed | - |
| heal.language | en | - |
| heal.publicationDate | 2010 | - |
| heal.recordProvider | Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής | el |
| heal.type | journalArticle | - |
| heal.type.el | Άρθρο Περιοδικού | el |
| heal.type.en | Journal article | en |
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