Multilevel Huffman coding: An efficient test-data compression method for IP cores

dc.contributor.authorKavousianos, X.en
dc.contributor.authorKalligeros, E.en
dc.contributor.authorNikolos, D.en
dc.date.accessioned2015-11-24T17:01:30Z
dc.date.available2015-11-24T17:01:30Z
dc.identifier.issn0278-0070-
dc.identifier.urihttps://olympias.lib.uoi.gr/jspui/handle/123456789/10937
dc.rightsDefault Licence-
dc.subjectembedded testing techniquesen
dc.subjecthuffman encodingen
dc.subjectintellectual property (ip) coresen
dc.subjectlinear feedback shift registers (lfsrs)en
dc.subjecttest-data compressionen
dc.subjectembedded deterministic testen
dc.subjecttwisted-ring countersen
dc.subjectbuilt-in-testen
dc.subjecta-chip testen
dc.subjectpattern generationen
dc.subjectscan chainsen
dc.subjectdata volumeen
dc.subjecttest timeen
dc.subjectreductionen
dc.subjectcircuitsen
dc.titleMultilevel Huffman coding: An efficient test-data compression method for IP coresen
heal.abstractA new test-data compression method suitable for cores of unknown structure is introduced in this paper. The proposed method encodes the test data provided by the core vendor using a new, very effective compression scheme based on multilevel Huffman coding. Each Huffman codeword corresponds to three different kinds of information, and thus, significant compression improvements compared to the already known techniques are achieved. A simple architecture is proposed for decoding the compressed data on chip. Its hardware overhead is very low and comparable to that of the most efficient methods in the literature. Moreover, the major part of the decompressor can be shared among different cores, which reduces the hardware overhead of the proposed architecture considerably. Additionally, the proposed technique offers increased probability of detection of unmodeled faults since the majority of the unknown values of the test sets are replaced by pseudorandom data generated by a linear feedback shift register.en
heal.accesscampus-
heal.fullTextAvailabilityTRUE-
heal.identifier.primaryDoi 10.1109/Tcad.2006.885830-
heal.journalNameIeee Transactions on Computer-Aided Design of Integrated Circuits and Systemsen
heal.journalTypepeer reviewed-
heal.languageen-
heal.publicationDate2007-
heal.recordProviderΠανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικήςel
heal.typejournalArticle-
heal.type.elΆρθρο Περιοδικούel
heal.type.enJournal articleen

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