A stress-relaxed negative voltage-level converter
Abstract
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peer reviewed
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Ieee Transactions on Circuits and Systems Ii-Express Briefs
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Description
In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-mu m triple-well standard CMOS technology, using double-gate-oxidethickness MOS transistors with an absolute maximum rating of 4.0 V, a nominal power supply of 1.8 V, and a required negative voltage of -3.3 V. Simulation results are provided to demonstrate the efficiency of the proposed topology. According to the results, 1.82-ns delay and 0.53-mW power consumption are reported.
Description
Keywords
embedded negative voltage-level converter, level shifter, level conversion, mos-device voltage stress relaxation, charge-pump circuits, flash memories, word-line, design, scheme, drams, cell, generator, eeprom, gate
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en
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Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής