SILC decay in La(2)O(3) gate dielectrics grown on Ge substrates subjected to constant voltage stress
| dc.contributor.author | Rahman, M. S. | en |
| dc.contributor.author | Evangelou, E. K. | en |
| dc.contributor.author | Androulidakis, I. I. | en |
| dc.contributor.author | Dimoulas, A. | en |
| dc.contributor.author | Mavrou, G. | en |
| dc.contributor.author | Galata, S. | en |
| dc.date.accessioned | 2015-11-24T18:35:32Z | |
| dc.date.available | 2015-11-24T18:35:32Z | |
| dc.identifier.issn | 0038-1101 | - |
| dc.identifier.uri | https://olympias.lib.uoi.gr/jspui/handle/123456789/17106 | |
| dc.rights | Default Licence | - |
| dc.subject | charge trapping | en |
| dc.subject | defects generation | en |
| dc.subject | silc | en |
| dc.subject | rare-earth oxides | en |
| dc.subject | la(2)o(3) | en |
| dc.subject | ge substrates | en |
| dc.subject | dielectric relaxation | en |
| dc.subject | cvs | en |
| dc.subject | induced leakage current | en |
| dc.subject | electron injection | en |
| dc.subject | trap generation | en |
| dc.subject | oxide-films | en |
| dc.subject | time-decay | en |
| dc.subject | breakdown | en |
| dc.subject | stacks | en |
| dc.subject | hfo2 | en |
| dc.subject | relaxation | en |
| dc.subject | interface | en |
| dc.title | SILC decay in La(2)O(3) gate dielectrics grown on Ge substrates subjected to constant voltage stress | en |
| heal.abstract | The effect of constant voltage stress (CVS) on Pt/La(2)O(3)/n-Ge MOS devices biased at accumulation is investigated and reported. It is found that the stress induced leakage current (SILC) initially increases due to electron charge trapping on pre-existing bulk oxide defects. After 10 s approximately, a clear decay of SILC commences which follows a t(-n) power law, with n lying between 0.56 and 0.75. This decay of SILC is not changed or reversed when the stressing voltage stops for short time intervals. The effect is attributed to the creation of new positively charged defects in the oxide because of the applied stressing voltage, while other mechanism such as dielectric relaxation proposed in the past is proved insufficient to explain the experimental data. Also high frequency capacitance vs. gate voltage (C-V(g)) curves measured under different CVS conditions divulge the creation of defects and charge trapping characteristics of La(2)O(3) preciously. At low CVS exemplify the generation positively charged defects, however at higher CVS charge trapping obeys a model that was previously proposed and is a continuous distribution of traps. (C) 2010 Elsevier Ltd. All rights reserved. | en |
| heal.access | campus | - |
| heal.fullTextAvailability | TRUE | - |
| heal.identifier.primary | DOI 10.1016/j.sse.2010.04.023 | - |
| heal.identifier.secondary | <Go to ISI>://000280322300025 | - |
| heal.identifier.secondary | http://ac.els-cdn.com/S0038110110001401/1-s2.0-S0038110110001401-main.pdf?_tid=8d8c326825565fdf4027f5c19c7807ce&acdnat=1334220064_8bf892907990f64279f3f34334850942 | - |
| heal.journalName | Solid-State Electronics | en |
| heal.journalType | peer reviewed | - |
| heal.language | en | - |
| heal.publicationDate | 2010 | - |
| heal.recordProvider | Πανεπιστήμιο Ιωαννίνων. Σχολή Επιστημών και Τεχνολογιών. Τμήμα Βιολογικών Εφαρμογών και Τεχνολογιών | el |
| heal.type | journalArticle | - |
| heal.type.el | Άρθρο Περιοδικού | el |
| heal.type.en | Journal article | en |
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