A high-density DRAM cell with built-in gain stage

dc.contributor.authorKamoulakos, G.en
dc.contributor.authorTsiatouhas, Y.en
dc.contributor.authorChrisanthopoulos, A.en
dc.contributor.authorArapoyanni, A.en
dc.date.accessioned2015-11-24T17:00:05Z
dc.date.available2015-11-24T17:00:05Z
dc.identifier.issn0018-9383-
dc.identifier.urihttps://olympias.lib.uoi.gr/jspui/handle/123456789/10705
dc.rightsDefault Licence-
dc.subjectmos devicesen
dc.subjectrandom access memoriesen
dc.subjectsemiconductor device modelingen
dc.subjectsemiconductor devicesen
dc.subjectsemiconductor memoriesen
dc.titleA high-density DRAM cell with built-in gain stageen
heal.abstractA high-density DRAM cell is proposed with a built-in vertical gain device topology. Due to the vertical built-in gain device, this cell exhibits increased reading speed, elongated refresh period, low-power oriented operation, and minor layout area penalty.en
heal.accesscampus-
heal.fullTextAvailabilityTRUE-
heal.journalNameIeee Transactions on Electron Devicesen
heal.journalTypepeer reviewed-
heal.languageen-
heal.publicationDate2001-
heal.recordProviderΠανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικήςel
heal.typejournalArticle-
heal.type.elΆρθρο Περιοδικούel
heal.type.enJournal articleen

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