Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands

Kavousianos, X.; Chakrabarty, K.; Jain, A.; Parekhji, R.

Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands

dc.contributor.author	Kavousianos, X.	en
dc.contributor.author	Chakrabarty, K.	en
dc.contributor.author	Jain, A.	en
dc.contributor.author	Parekhji, R.	en
dc.date.accessioned	2015-11-24T17:02:42Z
dc.date.available	2015-11-24T17:02:42Z
dc.identifier.issn	0278-0070	-
dc.identifier.uri	https://olympias.lib.uoi.gr/jspui/handle/123456789/11085
dc.rights	Default Licence	-
dc.subject	integer programming	en
dc.subject	linear programming	en
dc.subject	low-power electronics	en
dc.subject	multiprocessing systems	en
dc.subject	scheduling	en
dc.subject	system-on-chip	en
dc.subject	core switches	en
dc.subject	defect screening	en
dc.subject	dynamic voltage scaling	en
dc.subject	fast heuristic methods	en
dc.subject	integer linear programming	en
dc.subject	low power consumption	en
dc.subject	multicore system-on-chip	en
dc.subject	multivoltage domain testing	en
dc.subject	power supply voltage levels	en
dc.subject	state retention	en
dc.subject	test cost	en
dc.subject	test schedule optimization	en
dc.subject	test time	en
dc.subject	voltage islands	en
dc.subject	Complexity theory	en
dc.subject	Job shop scheduling	en
dc.subject	Multicore processing	en
dc.subject	Optimization	en
dc.subject	Schedules	en
dc.subject	System-on-a-chip	en
dc.subject	Testing	en
dc.subject	Core-based testing	en
dc.subject	SoC test scheduling	en
dc.subject	multicore systems-on-a-chip (SoCs)	en
dc.title	Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands	en
heal.abstract	In order to provide high performance with low power consumption, many multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage levels. Effective defect screening for such chips requires test applications at different operating voltages, which leads to higher test time and test cost compared to systems-on-a-chip (SoCs), which operate at only a single voltage level. We propose test scheduling techniques to minimize the testing time for multicore chips when each core is tested at multiple voltage levels and when it is tested for state retention when the core switches between two voltage levels. The proposed techniques include exact optimization based on integer linear programming and fast heuristic methods. Experimental results for two test-case SoCs from the industry highlight the effectiveness of the proposed method.	en
heal.access	campus	-
heal.fullTextAvailability	TRUE	-
heal.identifier.primary	10.1109/tcad.2012.2203600	-
heal.journalName	Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on	en
heal.journalType	peer reviewed	-
heal.publicationDate	2012	-
heal.recordProvider	Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής	el
heal.type	journalArticle	-
heal.type.el	Άρθρο Περιοδικού	el
heal.type.en	Journal article	en

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